CPU organization: general register and stack organization, RISC vs CISC, pipelining, vector processing and multiprocessor concepts. - One Line Questions

1. CISC (Complex Instruction Set Computer) architecture typically features: — Instructions that can perform complex operations and access memory directly
2. What is a 'superpipeline' in the context of CPU organization? — A pipeline with more stages, allowing for finer granularity and potentially higher clock speeds.
3. What is 'superscalar' architecture? — A processor with multiple execution units capable of executing multiple instructions per clock cycle.
4. Which of the following best describes the 'stack pointer' in a stack organization? — A register that points to the top element of the stack.
5. Multiprocessor systems involve: — Multiple independent CPUs that share memory and peripherals
6. What is a pipeline hazard? — A condition that prevents the next instruction from executing during its clock cycle
7. An instruction like 'ADD V1, V2, V3' in vector processing typically means: — Add corresponding elements of vector V2 and vector V3, storing the result in vector V1
8. Which of the following best describes the 'load-store' architecture prominent in RISC? — Only load and store instructions access memory; other operations work on registers.
9. In multiprocessor systems, a 'NUMA' (Non-Uniform Memory Access) architecture means: — Memory access time varies depending on the processor and the memory location.
10. Vector processors are particularly efficient for tasks involving: — Repetitive operations on large arrays of data
11. In RISC vs CISC, which architecture generally relies more heavily on the compiler to optimize instruction sequences? — RISC
12. In RISC (Reduced Instruction Set Computer) architecture, what is a key design principle? — Emphasis on memory-to-register operations
13. A branch instruction in a pipeline can cause which type of hazard? — Control hazard
14. In a pipelined processor, what is the 'fetch' stage responsible for? — Retrieving the instruction from memory
15. Which protocol is commonly used to maintain cache coherence in multiprocessor systems? — Snoopy cache protocols
16. In multiprocessor systems, what is cache coherence? — Maintaining consistency of data stored in multiple caches
17. What is pipelining in CPU organization? — Overlapping the execution stages of different instructions
18. Which of the following is NOT a typical stage in a basic CPU pipeline? — Cache Flush
19. Which type of CPU organization uses a limited number of registers and a stack pointer? — Stack Organization
20. Which type of processor organization is most closely associated with the 'accumulator' concept, where one operand is implicitly the accumulator? — Accumulator Organization
21. In a general register organization, how are operands typically specified in an instruction? — By register numbers or names
22. In a general register organization, what is the primary advantage of using registers? — Faster data manipulation and intermediate storage
23. Vector processing is designed to handle: — Independent instructions on multiple data elements simultaneously
24. Which of the following is a common issue in multiprocessor systems that requires synchronization mechanisms? — Race conditions when accessing shared resources
25. What is the main characteristic of a stack organization in CPU architecture? — Operands are implicitly accessed from the top of the stack
26. What is a potential challenge in multiprocessor systems related to resource sharing? — Difficulty in managing shared memory and avoiding race conditions
27. To resolve data hazards in a pipeline, techniques like 'forwarding' (or 'bypassing') are used. What does forwarding do? — It sends the result of an instruction directly from the execution stage to the input of another stage that needs it, without waiting for it to be written back to the register file.
28. How does a RISC processor typically handle complex operations that might be a single instruction in CISC? — It breaks down the complex operation into a sequence of simpler RISC instructions.
29. Which of the following is a characteristic of CISC processors? — Microprogrammed control unit
30. What is the primary advantage of vector processing over scalar processing for specific applications? — Higher throughput for data-parallel operations
31. What is the main difference between MIMD (Multiple Instruction, Multiple Data) and SIMD (Single Instruction, Multiple Data) multiprocessor systems? — MIMD systems have multiple processors executing different instructions on different data, while SIMD systems have multiple processors executing the same instruction on different data.
32. Which of the following is a characteristic of RISC processors? — More general-purpose registers
33. What is a key feature of SIMD (Single Instruction, Multiple Data) architecture, often used in vector processing? — A single control unit fetching and decoding instructions, but multiple processing units executing them on different data
34. What is the theoretical maximum speedup achievable by an ideal pipeline with 'n' stages for executing 'N' instructions? — n
35. What is a characteristic of tightly coupled multiprocessor systems? — Processors share a common clock and memory
36. In a stack organization, the 'call' instruction typically performs which actions? — Pushes the return address and parameters onto the stack.
37. Which of the following is a common technique to mitigate control hazards in pipelined processors? — Branch prediction
38. What is the main difference between tightly coupled and loosely coupled multiprocessor systems? — Communication mechanism
39. Which of the following is an advantage of CISC architecture? — Fewer instructions required to perform a task, potentially reducing program size
40. Which of the following is an advantage of RISC architecture? — Simpler instruction decoding
41. What is the primary benefit of RISC over CISC in terms of hardware? — Simpler instruction decoding and execution logic, leading to faster clock cycles and potentially more registers.
42. Which type of architecture is typically associated with supercomputers and scientific computing that perform the same operation on large datasets? — SIMD (Single Instruction, Multiple Data)
43. Which type of pipeline hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed? — Data hazard
44. What is 'instruction-level parallelism' (ILP) in superscalar processors? — The ability of the processor to execute multiple independent instructions from a single thread within the same clock cycle.
45. In a pipeline, what is 'instruction-level parallelism'? — The degree to which instructions within a single program can be executed in parallel.
46. In the context of pipelining, what is 'instruction fetch delay'? — The time taken to retrieve an instruction from memory, especially when there's a cache miss or a control hazard.
47. What is the primary goal of increasing the number of pipeline stages? — To allow for a higher clock frequency
48. What is the purpose of branch prediction in pipelined processors? — To reduce the impact of control hazards by guessing the outcome of branches
49. What is a 'structural hazard' in pipelining? — When two instructions need the same hardware resource at the same time.
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