Input–output organization, memory hierarchy (cache, virtual memory), memory management hardware and multicore processor issues. - One Line Questions

1. What is a 'memory segment' in some memory management schemes? — A contiguous block of memory that has a logical name and is treated as a unit
2. What is Virtual Memory? — A memory management technique that allows the execution of processes that are larger than the physical main memory
3. In a multi-core processor, what is a 'core'? — A complete processing unit capable of executing instructions independently
4. What is the 'working set' of a process in virtual memory management? — The set of pages that the process has accessed recently and is likely to access again soon
5. Which hardware component is responsible for managing memory access and protection in modern systems? — Memory Management Unit (MMU)
6. Which of the following statements about cache memory is TRUE? — Cache memory holds copies of recently accessed data from main memory.
7. Which of these is a characteristic of RISC (Reduced Instruction Set Computing) architecture that impacts I/O and memory organization? — Emphasis on load/store architecture, meaning memory access is primarily through explicit load and store instructions
8. Which of the following is NOT a typical component of the memory hierarchy? — Graphics Processing Unit (GPU)
9. Which protocol is commonly used to maintain cache coherence? — Snooping Protocols (e.g., MESI) or Directory-Based Protocols
10. Which of the following is a common technique used to manage shared caches in multi-core processors? — A hierarchical cache structure with shared last-level caches (LLC)
11. What is a significant challenge introduced by multi-core processors regarding memory? — Managing shared access to main memory and caches to avoid conflicts and maintain data consistency
12. Virtual memory typically uses which storage device for its 'backing store'? — Magnetic Hard Disk Drives (HDDs) or SSDs
13. In memory hierarchy, what is the trade-off between levels? — Faster levels are smaller and more expensive per bit; slower levels are larger and cheaper per bit.
14. Which of the following is a common page replacement algorithm? — First-In, First-Out (FIFO)
15. Which mapping technique for cache memory is the simplest to implement but can lead to conflicts? — Direct Mapping
16. Which type of memory is volatile and loses its content when power is turned off? — Random Access Memory (RAM)
17. Which of the following best describes the relationship between CPU speed and I/O speed? — CPU speeds have generally increased faster than I/O speeds, creating a 'CPU-I/O gap'.
18. In a multi-core processor, how can memory bandwidth become a bottleneck? — If the CPU cores can process data faster than it can be fetched from or written to memory.
19. Which of the following is a consequence of poor locality of reference in a virtual memory system? — Frequent page faults, leading to excessive disk I/O and slow performance
20. Which of the following is a fundamental issue when multiple cores share a single cache? — Potential for cache contention, where cores compete for cache space
21. Which of the following is a method for handling false sharing? — Padding data structures to ensure that data used by different cores is not on the same cache line
22. In a multi-processor system, if multiple processors need to access and potentially modify the same memory location, what mechanism is essential to prevent data corruption? — Cache coherence protocols and synchronization primitives (e.g., locks)
23. What is the main advantage of using virtual memory? — It allows for larger programs and more concurrent processes than physical memory alone would permit
24. Which level of the memory hierarchy is typically the fastest and smallest? — Registers
25. In a multi-level cache hierarchy (e.g., L1, L2, L3), where is L1 cache typically located? — On the CPU chip, closest to each individual core
26. In Fully Associative Mapping, where can a block from main memory be placed in the cache? — In any available location in the cache
27. Which I/O technique involves the CPU issuing a command and then continuing to execute other instructions without waiting for the I/O operation to complete? — Direct Memory Access (DMA)
28. Which type of I/O transfer is most suitable for high-speed peripherals like disk drives? — Direct Memory Access (DMA)
29. What is the 'locality of reference' principle, which is crucial for cache and virtual memory performance? — Programs tend to access memory locations that are spatially or temporally close to previously accessed locations
30. What is the typical relationship between the size and speed of memory levels in the hierarchy, from registers to secondary storage? — Size increases, speed decreases
31. In the context of I/O handling, what does polling involve? — The CPU continuously checking the status of an I/O device to see if it is ready for data transfer
32. Interrupt-driven I/O is generally more efficient than polling when: — The I/O device is slow and I/O operations are frequent
33. Consider a system with virtual memory. If a process needs to access a memory address, what is the first step in the translation process? — The MMU checks the TLB for a valid translation.
34. What does 'cache coherence' refer to in a multi-core system? — Ensuring that all cores have a consistent view of shared memory data, even when it's cached locally
35. What is the primary objective of a 'set-associative' cache mapping technique? — To allow a main memory block to map to a specific set of cache lines.
36. What is the purpose of a Memory Management Unit (MMU)? — To translate virtual memory addresses into physical memory addresses
37. Which of the following is a primary function of Input/Output (I/O) controllers? — To interface peripheral devices with the CPU and main memory
38. What is the primary goal of memory management hardware? — To facilitate efficient and safe sharing of memory among multiple processes
39. What is the role of an I/O channel or I/O processor? — To offload I/O management tasks from the main CPU, allowing it to focus on computation.
40. What is the primary role of the memory hierarchy in a computer system? — To reduce the average access time to memory by using multiple levels of storage with different speeds and costs
41. What is the main purpose of Direct Memory Access (DMA)? — To allow I/O devices to transfer data directly to and from main memory without CPU intervention
42. What is the purpose of a 'dirty bit' in a cache line or page table entry? — To indicate if the data in the cache/page has been modified since it was loaded from main memory
43. What is the principle behind cache memory? — To store frequently accessed data from main memory to reduce access time
44. What is the function of a Translation Lookaside Buffer (TLB)? — To cache recently used page table entries to speed up address translation
45. In memory management, what is the role of a 'page table'? — To map virtual page numbers to physical frame numbers
46. What is a 'page fault' in the context of virtual memory? — When the requested page is not currently in physical memory and must be loaded from secondary storage
47. What is a 'cache miss'? — When the requested data is NOT found in the cache and must be fetched from a lower level of the memory hierarchy
48. What is the 'thrashing' phenomenon in virtual memory systems? — When the system spends more time swapping pages in and out of memory than executing instructions
49. What is a 'false sharing' problem in multi-core processors? — When two cores modify different data items that happen to reside in the same cache line, causing unnecessary cache invalidations
50. What is the main difference between a write-through cache and a write-back cache? — Write-through updates main memory immediately; write-back updates main memory only when the cache block is replaced.
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