TRB PG Assistant - Flip-flops - RS, RST, JK, master–slave, ripple counters, decade counters, up–down counters, serial and parallel registers Online Test (MCQ Quiz)

1. What is the fundamental characteristic of a flip-flop?

A) It can store only one bit of information. B) It can store multiple bits of information. C) It performs arithmetic operations. D) It amplifies electronic signals.

2. Which type of flip-flop is the simplest bistable multivibrator?

A) JK Flip-Flop B) T Flip-Flop C) RS Flip-Flop D) D Flip-Flop

3. In an SR flip-flop, what is the state when both S (Set) and R (Reset) inputs are HIGH (1)?

A) Output Q is HIGH B) Output Q is LOW C) Invalid/Forbidden state D) Output toggles

4. What does the 'T' in T flip-flop stand for?

A) Toggle B) Trigger C) Transfer D) Test

5. Which input condition causes a T flip-flop to toggle its output state?

A) T = 0 B) T = 1 C) T = HIGH and LOW D) T = Clock pulse

6. What is the primary advantage of a JK flip-flop over an SR flip-flop?

A) It has fewer inputs. B) It resolves the indeterminate state of the SR flip-flop. C) It is slower in operation. D) It requires only one power supply.

7. In a JK flip-flop, when both J and K inputs are HIGH (1), what happens to the output on the clock edge?

A) It remains unchanged. B) It is set to HIGH. C) It is reset to LOW. D) It toggles.

8. What is the purpose of the 'master' in a master-slave flip-flop?

A) It receives inputs first and stores them. B) It receives the clock signal first. C) It directly drives the output. D) It is always in the reset state.

9. In a master-slave flip-flop, when does the 'slave' section get updated?

A) On the rising edge of the clock pulse. B) On the falling edge of the clock pulse. C) Simultaneously with the master. D) When the clock is HIGH.

10. What problem does the master-slave configuration primarily address in flip-flops?

A) Race around condition B) Power consumption C) Propagation delay D) Noise susceptibility

11. A ripple counter is also known as a:

A) Synchronous counter B) Asynchronous counter C) Shift register D) Decade counter

12. In a ripple counter, how is the clock input of each subsequent flip-flop connected?

A) To the main clock signal B) To the output of the previous flip-flop C) To the preset input of the previous flip-flop D) To the clear input of the previous flip-flop

13. What is the main disadvantage of a ripple counter compared to a synchronous counter?

A) Lower speed B) Higher power consumption C) More complex circuitry D) Requires more flip-flops

14. A counter that counts through a specific sequence of states, typically 0 to 9, is called a:

A) Ripple counter B) Up-down counter C) Decade counter D) Ring counter

15. How many flip-flops are minimally required to build a decade counter?

A) 2 B) 3 C) 4 D) 5

16. What is the modulus of a decade counter?

A) 8 B) 10 C) 16 D) 2

17. Which type of counter can count in both increasing and decreasing directions?

A) Ripple counter B) Decade counter C) Up-down counter D) Ring counter

18. What additional control input is typically required for an up-down counter?

A) Enable B) Mode select (Up/Down) C) Clear D) Preset

19. When the mode select input of an up-down counter is HIGH, it typically counts:

A) Down B) Up C) Stops counting D) Toggles

20. What is a register primarily used for?

A) Performing logic operations B) Storing a group of bits C) Amplifying signals D) Generating clock signals

21. In a serial register, data is entered and retrieved:

A) All at once B) One bit at a time C) In parallel D) In groups of four bits

22. Which type of register allows data to be input and output simultaneously, one bit after another?

A) SISO (Serial-In, Serial-Out) B) SIPO (Serial-In, Parallel-Out) C) PISO (Parallel-In, Serial-Out) D) PIPO (Parallel-In, Parallel-Out)

23. A SIPO register is commonly used for:

A) Parallel to serial conversion B) Serial to parallel conversion C) Data storage D) Arithmetic operations

24. In a parallel register, data is entered and retrieved:

A) One bit at a time B) In serial fashion C) All bits simultaneously D) In groups of two bits

25. A PIPO register is useful for:

A) Serial data transmission B) Temporary data storage where speed is critical C) Converting parallel data to serial D) Shifting data serially

26. Which register type allows data to be loaded in parallel and read out serially?

A) SISO B) SIPO C) PISO D) PIPO

27. A PISO register is primarily used for:

A) Serial to parallel conversion B) Parallel to serial conversion C) Data buffering D) Clock signal generation

28. What is the 'race around condition' primarily associated with?

A) SR flip-flops B) JK flip-flops operating in toggle mode with level triggering C) D flip-flops D) T flip-flops

29. Edge-triggered flip-flops are preferred over level-triggered flip-flops because they:

A) Are simpler to design B) Consume less power C) Avoid the race around condition D) Have faster output response

30. An RST flip-flop includes an additional input 'T' (Toggle). What happens when T=1?

A) The flip-flop is forced to state 0. B) The flip-flop is forced to state 1. C) The flip-flop toggles its output. D) The flip-flop remains in its current state.

31. What is the minimum number of flip-flops required to construct a counter that can count up to 15?

A) 2 B) 3 C) 4 D) 5

32. A counter that counts in the sequence 000, 001, 010, 011, 100, 101, 110, 111, 000... is a:

A) Decade counter B) Modulo-8 counter C) Modulo-16 counter (or Binary counter) D) Up-down counter

33. Which type of counter uses flip-flops that are all triggered simultaneously by the clock pulse?

A) Ripple counter B) Asynchronous counter C) Synchronous counter D) Shift register

34. What is a common application of shift registers?

A) Frequency division B) Data serialization and de-serialization C) Arithmetic addition D) Memory addressing

35. A Ring Counter is a type of:

A) Ripple counter B) Synchronous counter C) Shift register D) Decade counter

36. In a Ring Counter, how is the last flip-flop's output connected?

A) To the clock of the first flip-flop B) To the reset of the first flip-flop C) To the input of the first flip-flop D) To the output of the first flip-flop

37. What is the modulus of a standard 4-bit Ring Counter?

A) 4 B) 8 C) 16 D) 2

38. A Johnson Counter (or Twisted Ring Counter) is created by connecting the output of the last flip-flop to the ______ input of the first flip-flop.

A) Set B) Reset C) Complement (inverted output) D) Clock

39. What is the advantage of a Johnson Counter over a Ring Counter?

A) Higher speed B) Counts to a higher modulus using the same number of flip-flops C) Simpler design D) Lower power consumption

40. Which flip-flop is often used to implement a delay element in digital circuits?

A) SR Flip-Flop B) JK Flip-Flop C) T Flip-Flop D) D Flip-Flop

41. In a D flip-flop, the output Q takes the value of the D input on the:

A) Clock HIGH level B) Clock LOW level C) Rising edge of the clock pulse D) Falling edge of the clock pulse

42. What is the primary function of the 'preset' and 'clear' inputs on many flip-flops?

A) To control the clock speed B) To asynchronously set or reset the flip-flop's output C) To enable or disable the flip-flop D) To toggle the output state

43. Which counter type is most susceptible to glitches caused by propagation delays?

A) Synchronous counter B) Ripple counter C) Up-down counter D) Decade counter

44. What is the maximum frequency a ripple counter can reliably count at?

A) The clock frequency B) Half the clock frequency C) The clock frequency divided by the number of flip-flops D) Dependent on the fan-out

45. A universal shift register can perform:

A) Only serial shifts B) Only parallel transfers C) Both serial and parallel shifts, and potentially rotations D) Only counting operations

46. Which of the following is NOT a type of flip-flop?

A) SR B) JK C) XY D) D

47. What is the state table for an SR flip-flop with S=0 and R=0?

A) Q(next) = 1 B) Q(next) = 0 C) Q(next) = Q (no change) D) Q(next) = !Q (toggle)

48. Which counter design avoids the 'race around condition' by using edge-triggering?

A) Level-triggered JK flip-flop counter B) Master-slave JK flip-flop counter C) Ripple counter D) All counters using JK flip-flops

49. In a parallel-in/parallel-out (PIPO) shift register, all bits are loaded and read out:

A) Sequentially over time B) Simultaneously in one clock cycle C) Alternating between serial and parallel D) Based on an enable signal

50. Consider a 4-bit ripple counter counting up. If the current count is 1010 (binary), what will be the count after the next clock pulse?

A) 1011 B) 1100 C) 0111 D) 1001

Flip-flops - RS, RST, JK, master–slave, ripple counters, decade counters, up–down counters, serial and parallel registers - Online Test

Test Results