Basic Computer Organization and Design

Welcome to the foundational concepts of how computers are organized and designed. Understanding these basics is crucial for anyone delving into computer science, as it explains the fundamental workings of the machines we use every day. We will explore the core components and processes that make a computer function, starting with the concept of a stored program.

Stored Program Organization

Before the advent of the stored program concept, computers were programmed by physically rewiring them or setting switches. This was a cumbersome and time-consuming process. The breakthrough came with the idea that the instructions a computer executes, just like the data it processes, could be stored in its memory. This is the essence of the stored program organization, famously attributed to John von Neumann and his colleagues.

In a stored program computer, both program instructions and the data they operate on reside in the same memory space. The Central Processing Unit (CPU) fetches instructions from memory, decodes them, and then executes them. This fetched instruction might then cause the CPU to fetch data from memory, process it, and store the result back into memory. This cycle of fetching, decoding, and executing forms the basis of how a computer runs programs. This organization allows for much greater flexibility and efficiency, as programs can be easily loaded, changed, and executed without physical modifications to the hardware.

Instruction Codes

An instruction code is a binary code that tells the computer to perform a specific operation. It's the language the CPU understands. Each instruction code typically consists of two main parts: an opcode (operation code) and operands.

The opcode specifies the operation to be performed (e.g., add, subtract, load, store). The operands specify the data or locations of data on which the operation is to be performed. Operands can be memory addresses, register numbers, or immediate values.

Consider a simple instruction like "Add the number in memory location X to the number in register R1 and store the result in R1." This would be represented by an instruction code. The opcode would signify "ADD," and the operands would specify register R1 and memory location X.

Instruction codes can be of fixed length or variable length. In fixed-length instructions, all instructions have the same number of bits, making instruction fetching and decoding simpler. Variable-length instructions can be more efficient in terms of memory usage but complicate the control unit's design.

In a basic computer, instructions are often categorized into different types:

• Memory-Reference Instructions: These instructions operate on data stored in memory. Examples include LOAD (fetch data from memory to a register) and STORE (save data from a register to memory).
• Register-Reference Instructions: These instructions operate only on registers within the CPU. Examples include operations like moving data between registers or performing arithmetic on register contents.
• Input/Output Instructions: These instructions are used to communicate with peripheral devices.
• Control Instructions: These instructions affect the sequence of program execution, such as BRANCH (jump to a different instruction) or HALT (stop execution).

Computer Registers

Registers are small, high-speed storage locations within the CPU. They are used to hold data, instructions, addresses, and intermediate results that the CPU needs to access very quickly during processing. Because they are physically part of the CPU, accessing data in registers is significantly faster than accessing data in main memory.

Key registers in a basic computer organization include:

• Program Counter (PC): This register holds the address of the next instruction to be fetched from memory. It is automatically incremented after each instruction fetch.
• Instruction Register (IR): This register holds the instruction that has just been fetched from memory and is currently being decoded and executed.
• Accumulator (AC): This is a general-purpose register often used in arithmetic and logic operations. The result of an operation is frequently stored in the accumulator.
• Memory Address Register (MAR): This register holds the address of the memory location that the CPU wants to read from or write to.
• Memory Buffer Register (MBR): This register acts as a temporary storage area for data being transferred to or from memory. It holds the data read from memory or the data to be written to memory.
• General-Purpose Registers (R0, R1, etc.): Some computers have additional registers that can be used by the programmer for temporary storage of data or addresses.

Instruction Cycle

The instruction cycle, also known as the fetch-decode-execute cycle, is the fundamental sequence of operations that a CPU performs to execute a program. It consists of several phases:

1. Fetch Phase: The CPU fetches the next instruction from memory. The address of this instruction is stored in the Program Counter (PC). The PC's content is transferred to the Memory Address Register (MAR). The CPU then sends a read signal to memory. The instruction located at the address in MAR is retrieved and placed into the Memory Buffer Register (MBR). Finally, the instruction from MBR is transferred to the Instruction Register (IR). The PC is then incremented to point to the next instruction.
2. Decode Phase: The instruction in the IR is decoded by the control unit. This involves identifying the opcode and any operands to determine what operation needs to be performed and on what data.
3. Execute Phase: The control unit generates the necessary control signals to carry out the operation specified by the instruction. This might involve fetching data from memory, performing an arithmetic or logical operation using the ALU (Arithmetic Logic Unit), storing data back into memory, or branching to a different instruction.

This cycle repeats for every instruction in the program until the program is terminated (e.g., by a HALT instruction or an interrupt). Some complex instructions might require additional steps, such as operand fetch or result storage, which can extend the basic instruction cycle.

Timing and Control

The timing and control unit is a crucial component of the CPU that orchestrates the entire instruction cycle. It generates the sequence of control signals required for each step of the fetch, decode, and execute phases. These signals direct the flow of data between registers, the ALU, memory, and I/O devices.

The control unit typically uses a clock to synchronize its operations. The clock provides a series of pulses, and each pulse represents a basic time unit. The control unit interprets these pulses to control the timing of different micro-operations within the instruction cycle. For example, fetching an instruction might take several clock cycles, with different signals being generated at specific times to move data from PC to MAR, then to memory, and so on.

The control unit can be implemented in two ways:

• Hardwired Control: This is implemented using combinational logic circuits (gates and flip-flops). It's fast but inflexible, as changes to the instruction set require hardware redesign.
• Microprogrammed Control: In this approach, the control signals are stored in a special memory called a control memory. Each instruction is executed by a sequence of micro-instructions, where each micro-instruction specifies a set of control signals. This is more flexible, as the control program can be modified or expanded without changing the hardware.

The timing of operations is critical. For instance, a read operation from memory must be timed such that the data is available in the MBR before the next step that uses it can proceed. The control unit ensures these timing dependencies are met.

Memory-Reference Instructions

These are instructions that involve reading from or writing to the main memory. They are distinguished by their opcode, which indicates a memory operation. The operand part of these instructions typically contains the address of the memory location involved.

Common examples of memory-reference instructions include:

• LOAD: Fetches data from a specified memory address and places it into a CPU register (e.g., the Accumulator).

  Example: LOAD X - Reads the value from memory address X into the Accumulator.

• STORE: Takes data from a CPU register (e.g., the Accumulator) and writes it to a specified memory address.

  Example: STORE X - Writes the value from the Accumulator to memory address X.

• ADD: Reads data from a specified memory address, adds it to the value in the Accumulator, and stores the result back in the Accumulator.

  Example: ADD X - Accumulator = Accumulator + Memory[X]

• AND: Reads data from a specified memory address, performs a bitwise AND operation with the value in the Accumulator, and stores the result in the Accumulator.

  Example: AND X - Accumulator = Accumulator & Memory[X]

• BRANCH (or JUMP): Changes the flow of program execution by loading a new address into the Program Counter (PC). If the branch is conditional, the PC is updated only if a certain condition is met (e.g., the Accumulator is zero).

  Example: BRANCH X - Sets PC = X, causing the next instruction to be fetched from address X.

The effective address for these instructions is determined based on the addressing mode used. In a basic computer, direct addressing is common, where the address specified in the instruction is the actual memory address.

Input/Output (I/O)

Computers need to interact with the outside world through input and output devices (peripherals) like keyboards, displays, printers, and disk drives. The CPU communicates with these devices through specific I/O instructions.

There are two primary ways to handle I/O:

• Programmed I/O: In this method, the CPU uses special I/O instructions (like IN and OUT) to transfer data to or from I/O devices. The CPU must repeatedly check the status of the I/O device (e.g., is it ready to receive data?) using status bits. This can be inefficient as the CPU spends a lot of time waiting.
• Interrupt-Driven I/O: A more efficient method where the I/O device can signal the CPU when it is ready for data transfer or has completed an operation. This signal is called an interrupt. When an interrupt occurs, the CPU suspends its current task, handles the I/O request, and then resumes its original task. This frees up the CPU to perform other computations while waiting for I/O.

I/O devices are typically connected to the system through I/O controllers, which manage the communication between the device and the CPU/memory. Each I/O device often has a unique address or port number that the CPU uses in its I/O instructions.

Interrupts

An interrupt is a signal to the processor generated by hardware or software indicating an event that needs immediate attention. Interrupts are essential for efficient I/O handling and for responding to various system events.

When an interrupt occurs, the normal sequence of program execution is altered. The CPU stops executing the current program and transfers control to a special routine called an Interrupt Service Routine (ISR) or Interrupt Handler.

The process of handling an interrupt typically involves:

1. Interrupt Request: An I/O device (or other source) sends an interrupt signal to the CPU.
2. Interrupt Acknowledge: The CPU acknowledges the interrupt.
3. Context Save: The CPU saves the current state of the program it was executing. This includes the contents of the PC and other relevant registers. This is crucial so that the interrupted program can be resumed later from exactly where it left off.
4. Identify Interrupt Source: If multiple devices can generate interrupts, the CPU needs to determine which device triggered the interrupt.
5. Execute ISR: The CPU jumps to the specific Interrupt Service Routine (ISR) for that device and executes it. The ISR performs the necessary actions (e.g., reading data from the device).
6. Context Restore: After the ISR completes, the CPU restores the saved state of the interrupted program.
7. Resume Execution: The CPU resumes executing the interrupted program from the point it was stopped.

Interrupts can be classified based on their source:

• Hardware Interrupts: Generated by external hardware devices (e.g., I/O devices signaling completion, timer interrupts).
• Software Interrupts: Generated by executing a special instruction (often called a trap or software interrupt). These are often used for system calls, allowing user programs to request services from the operating system.

Interrupts can also be prioritized. High-priority interrupts (like power failure) might preempt lower-priority interrupts (like a key press). The CPU's ability to handle interrupts efficiently is a key factor in its performance and responsiveness.