Digital Logic Circuits and Components

Logic Gates

Logic gates are the fundamental building blocks of digital circuits. They perform basic logical operations on one or more binary inputs to produce a single binary output. These operations are based on Boolean algebra. The most common logic gates are AND, OR, NOT, NAND, NOR, XOR, and XNOR. Each gate has a specific truth table that defines its output for all possible combinations of inputs.

AND Gate

An AND gate outputs a HIGH (1) only if all of its inputs are HIGH. Otherwise, it outputs a LOW (0). It represents logical multiplication.

Symbol: A D-shaped symbol with inputs on the flat side and output on the curved side.

Truth Table (2-input):

Input A	Input B	Output Y
0	0	0
0	1	0
1	0	0
1	1	1

Boolean Expression: Y = A ⋅ B (or Y = AB)

OR Gate

An OR gate outputs a HIGH (1) if at least one of its inputs is HIGH. It outputs a LOW (0) only if all inputs are LOW. It represents logical addition.

Symbol: A shield-shaped symbol with a pointed input side and a curved output side.

Truth Table (2-input):

Input A	Input B	Output Y
0	0	0
0	1	1
1	0	1
1	1	1

Boolean Expression: Y = A + B

NOT Gate (Inverter)

A NOT gate has a single input and a single output. It inverts the input signal. If the input is HIGH, the output is LOW, and vice versa.

Symbol: A triangle with a small circle (bubble) at the output.

Truth Table (1-input):

Input A	Output Y
0	1
1	0

Boolean Expression: Y = A' (or Y = Ā)

NAND Gate

A NAND (NOT-AND) gate is an AND gate followed by a NOT gate. It outputs a LOW (0) only if all of its inputs are HIGH. Otherwise, it outputs a HIGH (1).

Symbol: An AND gate symbol with a bubble at the output.

Truth Table (2-input):

Input A	Input B	Output Y
0	0	1
0	1	1
1	0	1
1	1	0

Boolean Expression: Y = (A ⋅ B)'

NOR Gate

A NOR (NOT-OR) gate is an OR gate followed by a NOT gate. It outputs a HIGH (1) only if all of its inputs are LOW. Otherwise, it outputs a LOW (0).

Symbol: An OR gate symbol with a bubble at the output.

Truth Table (2-input):

Input A	Input B	Output Y
0	0	1
0	1	0
1	0	0
1	1	0

Boolean Expression: Y = (A + B)'

XOR Gate (Exclusive OR)

An XOR gate outputs a HIGH (1) if an odd number of its inputs are HIGH. It outputs a LOW (0) if an even number of its inputs are HIGH. It is useful for parity checking and arithmetic operations.

Symbol: An OR gate symbol with an additional curved line at the input side.

Truth Table (2-input):

Input A	Input B	Output Y
0	0	0
0	1	1
1	0	1
1	1	0

Boolean Expression: Y = A ⊕ B (or Y = A'B + AB')

XNOR Gate (Exclusive NOR)

An XNOR gate outputs a HIGH (1) if an even number of its inputs are HIGH. It outputs a LOW (0) if an odd number of its inputs are HIGH. It is the inverse of the XOR gate.

Symbol: An XOR gate symbol with a bubble at the output.

Truth Table (2-input):

Input A	Input B	Output Y
0	0	1
0	1	0
1	0	0
1	1	1

Boolean Expression: Y = (A ⊕ B)' (or Y = A'B' + AB)

Map Simplifications (Karnaugh Maps)

Karnaugh maps (K-maps) are a graphical method used to simplify Boolean algebra expressions. They are particularly effective for expressions with up to four or five variables. A K-map is a grid of cells, where each cell represents a minterm (a product term) of the Boolean function. Adjacent cells (horizontally or vertically) differ by only one variable.

How to use a K-map:

1. Create the K-map: Draw a grid. The number of cells is 2ⁿ, where 'n' is the number of variables. Label the rows and columns using Gray code (00, 01, 11, 10) to ensure adjacency.
2. Fill the K-map: For each minterm in the Boolean function (usually given in Sum of Products form), place a '1' in the corresponding cell of the K-map. For Product of Sums, place '0's. Unspecified terms are usually filled with 'X' (don't care).
3. Group the 1s (or 0s): Group adjacent '1's (or '0's) in powers of two (1, 2, 4, 8, etc.). Groups can wrap around the edges of the map. The goal is to form the largest possible groups.
4. Derive the simplified expression: For each group, identify the variables that remain constant within that group. If a variable is constant as '0', use its complemented form (e.g., A'). If it's constant as '1', use its uncomplemented form (e.g., A). The simplified term for the group is the product of these constant variables. The final simplified expression is the sum (for SOP) or product (for POS) of the terms derived from each group.

Example: Simplifying Y = Σm(0, 2, 3, 6, 7) with 3 variables (A, B, C)

The minterms are: 000, 010, 011, 110, 111.

3-variable K-map structure:

A\BC	00 (0)		01 (1)		11 (3)		10 (2)
0 (0)	1		0		0		1
1 (4)	0		0		1		1

Filling the map:

A\BC	00 (0)		01 (1)		11 (3)		10 (2)
0 (0)	1		0		1		1
1 (4)	0		0		1		1

Grouping:

• Group 1: Minterms 0, 2 (cells with 1 in rows A=0, columns BC=00 and BC=10). Here, A=0, B is irrelevant (0 and 1), C=0. Term: A'C'.
• Group 2: Minterms 2, 3, 6, 7 (cells with 1 in columns BC=10 and BC=11, rows A=0 and A=1). Here, A is irrelevant (0 and 1), B=1, C is irrelevant (0 and 1). Term: B.
• Group 3: Minterms 6, 7 (cells with 1 in rows A=1, columns BC=10 and BC=11). Here, A=1, B=1, C is irrelevant (0 and 1). Term: AB.

Simplified Expression (SOP): Y = A'C' + B + AB

Further simplification: Y = A'C' + B (since AB is covered by B).

Combinational Circuits

Combinational circuits are digital circuits whose output at any given time depends only on the current input values. They do not have memory elements; they do not store previous states. The output is a direct function of the input, like a mathematical function.

Common combinational circuits include:

• Adders (Half Adder, Full Adder)
• Subtractors
• Multiplexers (MUX)
• Demultiplexers (DEMUX)
• Encoders
• Decoders
• Comparators

Half Adder

A half adder is a combinational circuit that performs the addition of two single binary bits. It has two inputs (A and B) and two outputs: Sum (S) and Carry (C).

Input A	Input B	Sum (S)	Carry (C)
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Boolean Expressions: S = A ⊕ B, C = A ⋅ B

This means a half adder can be implemented using an XOR gate for the sum and an AND gate for the carry.

Full Adder

A full adder is a combinational circuit that adds three single binary bits: two input bits (A and B) and a Carry-in bit (Cin). It produces a Sum (S) output and a Carry-out bit (Cout). Full adders are used to build multi-bit adders.

Input A	Input B	Carry In (Cin)	Sum (S)	Carry Out (Cout)
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Boolean Expressions:

S = A ⊕ B ⊕ Cin

Cout = (A ⋅ B) + (Cin ⋅ (A ⊕ B))

A full adder can be constructed using two half adders and an OR gate.

Flip-Flops

Flip-flops are the basic memory elements in sequential circuits. Unlike combinational circuits, flip-flops have memory; they can store a single bit of information. Their output depends not only on the current inputs but also on the previous state of the circuit. Flip-flops are typically controlled by a clock signal.

Types of Flip-Flops:

Flip-flops are categorized based on their triggering mechanism (level-triggered or edge-triggered) and their inputs.

1. SR Flip-Flop (Set-Reset)

The basic SR flip-flop has two inputs, S (Set) and R (Reset). When S=1 and R=0, the output Q becomes 1 (Set state). When S=0 and R=1, the output Q becomes 0 (Reset state). If S=0 and R=0, the output remains unchanged (Hold state). The input combination S=1, R=1 is invalid as it leads to complementary outputs.

Operation (Characteristic Table):

S	R	Next State (Q)	Comment
0	0	Q	Hold
0	1	0	Reset
1	0	1	Set
1	1	Invalid	Forbidden

SR flip-flops can be implemented using NAND or NOR gates.

2. Gated SR Flip-Flop

This is an SR flip-flop with an additional Enable (E) or Clock (CLK) input. The flip-flop only responds to S and R inputs when the Enable signal is HIGH.

Boolean Expression:

Q_next = S ⋅ E + Q ⋅ E'

Q'_next = R ⋅ E + Q' ⋅ E'

3. JK Flip-Flop

The JK flip-flop is an improvement over the SR flip-flop. It has inputs J and K. It behaves like an SR flip-flop for J=0, K=0 (Hold) and J=1, K=0 (Set) or J=0, K=1 (Reset). The key difference is that when J=1 and K=1, the output toggles (flips) to its opposite state. This eliminates the invalid state of the SR flip-flop.

Operation (Characteristic Table):

J	K	Next State (Q)	Comment
0	0	Q	Hold
0	1	0	Reset
1	0	1	Set
1	1	Q'	Toggle

Characteristic Equation: Q_next = J ⋅ Q' + K' ⋅ Q

4. T Flip-Flop (Toggle)

The T flip-flop is a special case of the JK flip-flop where J and K are tied together (J=K=T). If T=0, the output holds its state. If T=1, the output toggles.

Operation (Characteristic Table):

T	Next State (Q)	Comment
0	Q	Hold
1	Q'	Toggle

Characteristic Equation: Q_next = T ⊕ Q

A T flip-flop is useful for creating counters.

5. D Flip-Flop (Delay)

The D flip-flop has a single data input D. The output Q takes the value of the D input after the clock edge. It essentially delays the data input by one clock cycle.

Operation (Characteristic Table):

D	Next State (Q)	Comment
0	0	Stored 0
1	1	Stored 1

Characteristic Equation: Q_next = D

D flip-flops are widely used in shift registers and memory. They are often implemented using gated SR or JK flip-flops.

Clocking and Triggering:

Most flip-flops are synchronous, meaning their state changes only occur at specific times determined by a clock signal.

• Level-Triggered: The flip-flop responds to input changes as long as the clock signal is at a certain level (e.g., HIGH).
• Edge-Triggered: The flip-flop responds to input changes only at the transition (edge) of the clock signal – either the rising edge (0 to 1) or the falling edge (1 to 0). This is generally preferred for avoiding timing issues.

Sequential Circuits

Sequential circuits are digital circuits whose output depends not only on the current input but also on the past sequence of inputs. This is achieved by incorporating memory elements, typically flip-flops. Sequential circuits have feedback paths, allowing information to be stored and reused.

There are two main types of sequential circuits:

• Asynchronous Sequential Circuits: These circuits do not use a clock signal. State changes occur immediately when inputs change, based on the propagation delays of the gates. They are simpler in terms of clocking but harder to design and analyze due to timing issues.
• Synchronous Sequential Circuits: These circuits use a clock signal to synchronize state changes. All memory elements (flip-flops) change their state simultaneously on the clock edge. This makes them easier to design, analyze, and less prone to timing problems. Most practical sequential circuits are synchronous.

The design of sequential circuits involves:

1. Defining the states and transitions (State Diagram).
2. Deriving the state table.
3. Assigning flip-flop states (State Assignment).
4. Deriving flip-flop input equations and output equations using K-maps or Boolean algebra.
5. Implementing the circuit using flip-flops and logic gates.

Decoders

A decoder is a combinational circuit that converts a binary input code into a unique output signal. It has 'n' input lines and up to 2ⁿ output lines. For each unique 'n'-bit binary input combination, exactly one of the output lines is activated (usually set to HIGH).

Example: 2-to-4 Decoder

This decoder has 2 input lines (A, B) and 4 output lines (D0, D1, D2, D3).

Input A	Input B	Output D0	Output D1	Output D2	Output D3
0	0	1	0	0	0
0	1	0	1	0	0
1	0	0	0	1	0
1	1	0	0	0	1

Boolean Expressions:

D0 = A' ⋅ B'

D1 = A' ⋅ B

D2 = A ⋅ B'

D3 = A ⋅ B

Decoders are used in memory addressing, instruction decoding, and display drivers.

Multiplexers (MUX)

A multiplexer is a combinational circuit that selects one of several input lines and routes it to a single output line. It has data inputs, selection lines, and one output. The number of selection lines determines how many data inputs the MUX can handle (2^s inputs, where 's' is the number of selection lines).

Example: 4-to-1 Multiplexer

This MUX has 4 data inputs (I0, I1, I2, I3), 2 selection lines (S1, S0), and 1 output (Y). The combination of S1 and S0 determines which input is passed to the output.

S1	S0	Selected Input	Output Y
0	0	I0	I0
0	1	I1	I1
1	0	I2	I2
1	1	I3	I3

Boolean Expression:

Y = I0 ⋅ S1' ⋅ S0' + I1 ⋅ S1' ⋅ S0 + I2 ⋅ S1 ⋅ S0' + I3 ⋅ S1 ⋅ S0

Multiplexers are often called "data selectors" and are used in data routing, parallel-to-serial conversion, and implementing Boolean functions.

Registers

A register is a sequential circuit used for storing a group of bits. It is typically composed of a set of flip-flops, where each flip-flop stores one bit. The number of flip-flops in a register determines the number of bits it can store (e.g., an 8-bit register has 8 flip-flops). Registers are essential components in the CPU for holding data, instructions, and addresses.

Types of Registers:

• SISO (Serial-In, Serial-Out) Register: Data is entered serially (one bit at a time) and retrieved serially. This is essentially a shift register.
• SIPO (Serial-In, Parallel-Out) Register: Data is entered serially, but all bits can be read out in parallel simultaneously.
• PISO (Parallel-In, Serial-Out) Register: Data is entered in parallel (all bits at once), and retrieved serially.
• PIPO (Parallel-In, Parallel-Out) Register: Data is entered in parallel and retrieved in parallel. This is the simplest type and is often used for temporary data storage.
• Shift Registers: These are a special type of register where the flip-flops are connected in a chain, allowing the stored data to be shifted left or right with each clock pulse. They are fundamental for serial-to-parallel and parallel-to-serial data conversion.

Example: 4-bit PIPO Register using D Flip-Flops

A 4-bit PIPO register consists of four D flip-flops. Each flip-flop receives one bit of the input data (D3, D2, D1, D0) and one clock signal. The outputs (Q3, Q2, Q1, Q0) hold the stored bits.

If the clock is pulsed, the data present at the D inputs is transferred to the Q outputs and stored.

Example: 4-bit SISO Shift Register (Right Shift)

Uses four D flip-flops connected in series. The output of each flip-flop (except the last) is connected to the data input of the next flip-flop.

Let the flip-flops be FF3, FF2, FF1, FF0.

Input to FF3 = Serial Data Input (Din)

Input to FF2 = Output of FF3 (Q3)

Input to FF1 = Output of FF2 (Q2)

Input to FF0 = Output of FF1 (Q1)

Output = Output of FF0 (Q0)

On each clock pulse, the data shifts one position to the right. The last bit (Q0) is shifted out and lost. A new bit enters at Din.

Counters

Counters are sequential circuits that count a sequence of events, usually represented by clock pulses. They are built using flip-flops and logic gates. The output of a counter represents the number of clock pulses that have occurred.

Types of Counters:

• Asynchronous (Ripple) Counters: In these counters, the output of one flip-flop drives the clock input of the next flip-flop. They are simpler but suffer from propagation delay ("ripple effect"), making them slower and potentially inaccurate for high frequencies.
• Synchronous Counters: In these counters, all flip-flops are driven by a common clock signal. This ensures that all state changes happen simultaneously, making them faster and more reliable. They require more complex logic to determine the next state.

Counter Operation:

• Up Counter: Counts in increasing order (0, 1, 2, 3...).
• Down Counter: Counts in decreasing order (3, 2, 1, 0...).
• Up/Down Counter: Can be configured to count either up or down.
• Modulus (Modulo) Counter: A counter that counts up to a certain number 'M' and then resets. It has 'M' states. For example, a Mod-3 counter counts 0, 1, 2 and then resets to 0.

Example: 2-bit Asynchronous Up Counter

Uses two T flip-flops (or JK flip-flops configured as T). Let the flip-flops be FF1 (LSB) and FF0 (MSB).

FF1: T1 = 1 (always toggles). Clock input is the external clock.

FF0: T0 = 1 (always toggles). Clock input is the output Q1 of FF1.

Sequence:

Clock Pulse	FF1 (Q1)	FF0 (Q0)	Count (Q1Q0)
Initial	0	0	00
1	1	0	01
2	0	1	10
3	1	1	11
4	0	0	00 (Resets)

This is a Mod-4 counter.

Example: 3-bit Synchronous Up Counter

Uses three JK flip-flops (FF2, FF1, FF0) clocked by a common clock.

State Table:

Current State (Q2Q1Q0)	Next State (Q2Q1Q0)	Flip-Flop Inputs (J2K2, J1K1, J0K0)
000	001	00, 00, 11
001	010	00, 11, 00
010	011	00, 00, 11
011	100	11, 10, 00
100	101	00, 00, 11
101	110	00, 11, 00
110	111	00, 00, 11
111	000	11, 10, 00

The flip-flop inputs (J and K) are determined based on the current state and the desired next state, using K-maps to derive the logic. For example, J0=K0=1 for all states except when the counter needs to hold (which it doesn't in a simple up counter). J1=1 only when Q0=1. K1=1 only when Q0=1. J2=1 only when Q1=1 and Q0=1. K2=1 only when Q1=1 and Q0=1.

Memory Unit

In computer architecture, a memory unit is a device capable of storing digital information. It consists of a large number of storage cells, each capable of storing one bit. Memory units are organized into words, where each word has a specific number of bits (e.g., 8 bits, 16 bits, 32 bits).

Types of Memory:

• Random Access Memory (RAM): RAM is volatile memory, meaning its contents are lost when power is turned off. It allows data to be read from and written to any location with approximately equal access time. RAM is used for main memory (working memory) in computers.
  • Static RAM (SRAM): Uses flip-flops to store each bit. It is faster than DRAM but more expensive and less dense.
  • Dynamic RAM (DRAM): Uses capacitors to store each bit. Capacitors leak charge over time, requiring periodic refreshing. It is slower but cheaper, denser, and consumes less power per bit than SRAM.
• Read-Only Memory (ROM): ROM is non-volatile memory, meaning its contents are retained even when power is off. Data is written to ROM during manufacturing or a special programming process and can only be read.
  • PROM (Programmable ROM): Can be programmed once by the user.
  • EPROM (Erasable Programmable ROM): Can be erased using ultraviolet light and reprogrammed.
  • EEPROM (Electrically Erasable Programmable ROM): Can be erased and reprogrammed electrically, byte by byte.
  • Flash Memory: A type of EEPROM that can be erased and reprogrammed in blocks, offering higher density and faster erase/write times. Used in SSDs, USB drives, and memory cards.

Memory Organization:

Memory is organized as a grid of cells. Each cell can store a bit. A memory unit with 'N' words and 'W' bits per word has N x W storage cells.

Addressing: Each word in memory has a unique address. If there are 'N' words, there are 'N' possible addresses. To access 'N' words, you need 'm' address lines such that 2^m = N.

Memory Read Operation:

1. The CPU places the desired memory address on the address bus.
2. The CPU asserts the Read control signal.
3. The memory unit decodes the address to select the specified word.
4. The data from the selected word is placed on the data bus.
5. The CPU reads the data from the data bus.

Memory Write Operation:

1. The CPU places the desired memory address on the address bus.
2. The CPU places the data to be written on the data bus.
3. The CPU asserts the Write control signal.
4. The memory unit decodes the address to select the specified word.
5. The data from the data bus is written into the selected word's storage cells.