Input-Output (I/O) Organization

In any computer system, the Central Processing Unit (CPU) and the Main Memory are responsible for processing and storing data. However, for the system to be useful, it needs to interact with the outside world. This interaction is facilitated by Input/Output (I/O) devices. Input devices allow data and instructions to enter the computer, while output devices display or present the processed results. The Input-Output Organization section of computer architecture deals with how the CPU communicates with these peripheral devices.

Peripheral Devices

Peripheral devices are external hardware components that connect to a computer to expand its capabilities. They are not part of the core computer system (CPU, memory, motherboard) but are essential for user interaction and data management. These devices can be broadly categorized into input devices, output devices, and storage devices.

Input Devices

Input devices translate information from the outside world into binary code that the computer can understand.

• Keyboard: The most common input device, used to enter text and commands.
• Mouse: A pointing device used to interact with graphical user interfaces (GUIs).
• Scanner: Converts hard copy documents or images into digital format.
• Microphone: Captures audio input.
• Webcam: Captures video input.
• Joystick/Gamepad: Used for gaming and simulation.

Output Devices

Output devices translate the binary information processed by the computer into a human-readable format or an external action.

• Monitor/Display: Visual output of text, graphics, and video.
• Printer: Produces hard copies of documents.
• Speakers: Produce audio output.
• Projector: Displays computer output onto a large screen.
• Plotter: Used for creating large-format drawings and graphics.

Storage Devices (Secondary Storage)

While primary memory (RAM) is volatile and used for active data, secondary storage devices provide non-volatile storage for large amounts of data and programs.

• Hard Disk Drive (HDD): Magnetic storage for large data volumes.
• Solid State Drive (SSD): Faster storage using flash memory.
• USB Flash Drive: Portable flash memory storage.
• Optical Discs (CD/DVD/Blu-ray): Use lasers to read/write data.

I/O Interface

The I/O interface is the hardware and software logic that connects a peripheral device to the computer's internal bus system (address bus, data bus, control bus). It acts as a translator and controller, managing the data transfer between the CPU/memory and the peripheral. Each I/O device typically requires a dedicated I/O interface module.

An I/O interface typically consists of:

• Data Registers: To hold data being transferred to or from the peripheral.
• Control Registers: To store commands from the CPU to the device or status information from the device to the CPU.
• Status Registers: To indicate the current state of the device (e.g., busy, ready, error).
• Control Logic: To interpret commands and manage the data transfer protocol.
• Interface Circuits: To handle the physical connection and signal conversion for the specific peripheral.

The CPU communicates with the I/O interface using I/O instructions, such as `IN` and `OUT`, which specify the device address and transfer data.

Asynchronous Data Transfer

In computer systems, data transfer can be synchronous or asynchronous. Synchronous transfer relies on a common clock signal to synchronize the sender and receiver. Asynchronous transfer, on the other hand, does not use a common clock. Instead, it uses control signals to coordinate the transfer of data between the sender and receiver. This is particularly useful when the speed of the peripheral device is different from the speed of the CPU or main memory.

Asynchronous data transfer typically involves two main control signals:

• Strobe Control: A single control line (strobe) is used to indicate that the data is valid. The sender places data on the bus and then asserts the strobe signal. The receiver detects the strobe signal and reads the data. The strobe signal is then de-asserted. This method works well when the sender and receiver operate at similar speeds or when the sender can wait for the receiver to acknowledge.
• Handshake Control: This is a more robust method that uses two control signals to ensure reliable data transfer between devices of different speeds. It involves an active communication exchange between the sender and receiver.
  • Source (Sender) signals: 'Data Valid' (indicates data is ready on the bus).
  • Destination (Receiver) signals: 'Data Accepted' (indicates data has been read and accepted).
  The process:
  1. The source places data on the bus.
  2. The source asserts 'Data Valid'.
  3. The destination detects 'Data Valid', reads the data, and asserts 'Data Accepted'.
  4. The source detects 'Data Accepted', de-asserts 'Data Valid' (and removes data), and de-asserts 'Data Valid'.
  5. The destination detects the de-assertion of 'Data Valid' and de-asserts 'Data Accepted'.
  This handshake ensures that data is only transferred when both devices are ready.

  Modes of Transfer

  There are several ways data can be transferred between the main memory and peripheral devices. The choice of mode depends on the amount of data, the speed of the devices, and the desired CPU involvement.

  1. Programmed I/O (PIO)

  In Programmed I/O, the CPU is directly responsible for initiating and managing every I/O transfer. The CPU executes I/O instructions that move data between CPU registers and the I/O interface. The CPU continuously checks the status of the I/O device (using status registers) to see if it is ready to send or receive data.

  Process:

  1. CPU issues a command to the I/O device.
  2. CPU repeatedly checks the device's status flag (e.g., 'Ready' or 'Busy') using status read instructions.
  3. Once the device is ready, the CPU issues a read/write instruction to transfer data between a CPU register and the device's data register.
  4. This process repeats for every unit of data (e.g., byte or word).

  Advantages: Simple to implement.

  Disadvantages: CPU spends most of its time polling the device status, leading to inefficient CPU utilization, especially for slow devices.

  2. Interrupt-Initiated I/O

  To overcome the inefficiency of Programmed I/O, interrupt-initiated I/O allows the I/O device to signal the CPU when it is ready for a data transfer. When the device is ready, it sends an interrupt request (IRQ) signal to the CPU. The CPU temporarily suspends its current task, saves its state, and executes a special subroutine called an Interrupt Service Routine (ISR) to handle the I/O transfer. After the ISR completes, the CPU resumes its original task.

  Process:

  1. CPU issues a command to the I/O device and then continues with its program.
  2. The I/O device performs its operation. When ready for data transfer, it sends an interrupt signal to the CPU.
  3. CPU acknowledges the interrupt, suspends its current program, and jumps to the ISR.
  4. The ISR handles the data transfer (e.g., reads a byte from the device).
  5. The ISR returns control to the CPU, which resumes its original program from where it left off.

  Advantages: More efficient CPU utilization as the CPU is not constantly polling.

  Disadvantages: Requires interrupt handling hardware and software, which adds complexity. Overhead associated with saving and restoring CPU state for each interrupt.

  3. Direct Memory Access (DMA)

  Direct Memory Access (DMA) is the most efficient mode for transferring large blocks of data. In DMA, a special hardware component called a DMA controller (DMAC) takes over the control of data transfer between the I/O device and the main memory. The CPU initiates the transfer by providing the DMAC with the memory address, the I/O device, the number of words to transfer, and the direction of transfer. Once initiated, the CPU is free to perform other tasks while the DMAC handles the entire block transfer directly, without further CPU intervention.

  Process:

  1. CPU initializes the DMAC by providing the starting memory address, the I/O device address, the number of words to transfer, and the transfer direction.
  2. CPU then continues with its own tasks.
  3. The DMAC takes control of the system bus (temporarily "stealing" cycles from the CPU) and transfers the block of data between the I/O device and memory.
  4. Once the transfer is complete, the DMAC sends an interrupt signal to the CPU to notify it.

  Advantages: Very high data transfer rates, minimal CPU involvement during transfer, leading to maximum CPU utilization for other tasks.

  Disadvantages: Requires a dedicated DMA controller, which adds hardware cost and complexity. Bus arbitration is needed to manage bus access between the CPU and DMAC.

  Priority Interrupt

  In a system with multiple I/O devices, it's possible for several devices to request an interrupt simultaneously. To handle this, a priority interrupt system is implemented. This system assigns different priority levels to various interrupt sources. When multiple interrupts occur at the same time, the interrupt with the highest priority is serviced first.

  There are two main approaches to implementing priority interrupts:

  1. Software Methods (Polling)

  In this method, the CPU, after receiving an interrupt signal, checks a list of interrupt sources in a specific order (defined by priority) to determine which device requested the interrupt.

  • Vectored Interrupts: When an interrupt occurs, the interrupting device provides a unique "vector" (an address or an offset) that points to the ISR for that specific device. The CPU uses this vector to directly jump to the correct ISR. Higher priority devices can be assigned vectors that lead to higher priority ISRs.
  • Non-Vectored Interrupts: In this case, all devices interrupt the CPU through a single input. The CPU then needs to poll or check each device to identify the source. The order in which the CPU polls determines the priority. The CPU checks the highest priority device first. If it's the source, its ISR is executed. If not, it checks the next highest priority device, and so on.

  2. Hardware Methods

  Hardware priority logic is more efficient than software polling. It uses dedicated hardware circuits to manage interrupt priorities.

  • Daisy Chaining: This is a common hardware method. Interrupt request lines from devices are connected together, and an interrupt acknowledge signal is passed from one device to the next in a serial fashion (like a chain). The device with the highest priority is connected first in the chain. When an interrupt occurs, the CPU sends an interrupt acknowledge signal. This signal travels down the chain. The first device that requested an interrupt and is enabled to do so will capture the acknowledge signal and send its interrupt vector to the CPU. Higher priority devices are placed closer to the CPU in the chain.
  • Parallel Priority Scheme: In this method, each interrupt input has a separate priority encoder circuit. The encoder generates a binary code representing the highest priority interrupt request. This scheme is faster but requires more hardware.

  Interrupt Priority Levels: Devices are assigned priority levels. A higher priority interrupt can interrupt a lower priority interrupt service routine. However, a lower priority interrupt cannot interrupt a higher priority interrupt service routine.

  Direct Memory Access (DMA) - In Depth

  As mentioned earlier, DMA is crucial for high-speed data transfer. Let's look at its components and operation in more detail.

  DMA Controller (DMAC): This is a specialized hardware component that acts as a dedicated processor for I/O transfers. It contains registers for storing:

  • Address Register: The starting memory address for the transfer.
  • Word Count Register: The number of words (bytes or blocks) to be transferred.
  • Control Register: Specifies the mode of transfer (e.g., read from I/O to memory, write from memory to I/O), device selection, and transfer direction.
  • Current Address Register: Keeps track of the current memory address being accessed during the transfer.

  Bus Master/Bus Slave: The DMAC acts as a "bus master." This means it can request control of the system bus (address bus, data bus, and control bus) from the CPU. The CPU acts as the "bus slave" in this context.

  Bus Arbitration: When both the CPU and the DMAC need to use the system bus simultaneously, a bus arbitration mechanism is required. This mechanism decides which device gets control of the bus. Common arbitration methods include:

  • Daisy Chaining: Similar to interrupt daisy chaining, a priority is established.
  • Independent Request: Each device has separate request and grant lines to an external arbiter.
  • Centralized Arbitration: A single arbiter controls bus access.

  DMA Transfer Modes:

  • Burst Mode: The DMAC gains control of the bus and transfers the entire block of data without releasing it until the transfer is complete. This is the fastest mode but temporarily halts CPU operation.
  • Cycle Stealing Mode: The DMAC requests the bus for one word transfer at a time. It steals bus cycles from the CPU. The CPU continues its operations, but its execution is slowed down as it waits for the DMAC to complete each word transfer. This is a compromise between transfer speed and CPU availability.
  • Transparent Mode: The DMAC transfers data only when the CPU does not need the bus. This is the slowest but allows the CPU to run at full speed when it needs the bus.

  DMA Controller Operation Example (Read from I/O to Memory):

  1. CPU initializes DMAC: sets memory address, word count, selects I/O device, sets direction (I/O to Memory).
  2. DMAC requests bus control.
  3. Bus arbiter grants bus control to DMAC.
  4. DMAC places the I/O device address on the address bus and issues a read command.
  5. DMAC reads data from the I/O device.
  6. DMAC places the memory address on the address bus and issues a write command.
  7. DMAC writes the data to the specified memory location.
  8. DMAC decrements word count and increments memory address.
  9. Steps 3-7 repeat until word count reaches zero.
  10. DMAC relinquishes bus control.
  11. DMAC sends an interrupt to the CPU indicating completion.

  DMA Shortcut:

  Think of DMA as a dedicated delivery service for large packages (data blocks). The CPU places an order (initializes DMAC) and then goes back to its own work. The delivery service (DMAC) handles the pickup (from I/O) and delivery (to memory) directly, only notifying the CPU when the job is done.

  Serial Communication

  Serial communication is a method of transmitting data one bit at a time over a single communication line or channel. This is in contrast to parallel communication, where multiple bits are transmitted simultaneously over multiple lines. Serial communication is often used for long-distance transmission or when the cost of cabling is a concern.

  Key Concepts:

  • Baud Rate: The speed of serial communication, representing the number of signal changes (or symbols) per second. Often confused with bits per second (bps), but technically represents symbol rate. For simple schemes like NRZ, baud rate equals bps.
  • Data Bits: The number of bits that constitute a single character or data unit (commonly 7 or 8 bits).
  • Parity Bit: An optional bit used for error detection. It can be even parity (number of 1s is even) or odd parity (number of 1s is odd).
  • Stop Bits: One or more bits added at the end of a data unit to signal the end of transmission and allow the receiver to resynchronize.

  Types of Serial Communication:

  • Asynchronous Serial Communication: Data is transmitted one character at a time, with start and stop bits framing each character. The timing between characters is not strictly controlled by a clock, but the receiver synchronizes with the start bit of each character. This is widely used in modems, terminals, and microcontrollers (e.g., UART).
  • Synchronous Serial Communication: Data is transmitted in a continuous stream of bits, synchronized by a common clock signal shared between the sender and receiver. This method is more efficient for large data transfers as it avoids the overhead of start/stop bits for every character. Examples include SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit).

  Serial Interface Standards:

  • RS-232: A widely used standard for serial communication, defining voltage levels, pinouts, and connector types. It's common for connecting modems, printers, and older computer peripherals.
  • RS-422/RS-485: Differential signaling standards offering better noise immunity and longer cable lengths compared to RS-232, suitable for industrial environments.
  • USB (Universal Serial Bus): A modern standard that supports both serial data transmission and power delivery, widely used for connecting peripherals like keyboards, mice, printers, and external storage.
  • Ethernet: While often considered a networking standard, it uses serial transmission over twisted-pair or fiber optic cables.

  Universal Asynchronous Receiver/Transmitter (UART): A common hardware component found in microcontrollers and computer systems that handles asynchronous serial communication. It converts parallel data from the CPU into serial bits for transmission and converts incoming serial bits back into parallel data for the CPU.

  Universal Synchronous/Asynchronous Receiver/Transmitter (USART): A more advanced version of UART that supports both synchronous and asynchronous modes.

  Serial vs. Parallel:

  Serial: One bit at a time, single wire, slower but cheaper for long distances. (Think of a single-lane road).

  Parallel: Multiple bits at a time, multiple wires, faster but more expensive and prone to timing issues (skew) over distance. (Think of a multi-lane highway).