TRB PG Assistant - Input-Output Organization - peripheral devices, I-O interface, asynchronous data transfer, modes of transfer, priority interrupt, DMA, serial communication Online Test (MCQ Quiz)

1. Which of the following is a primary characteristic of a peripheral device in a computer system?

A) It is essential for the CPU to function. B) It allows the computer to interact with the external environment. C) It performs complex arithmetic operations. D) It stores the operating system.

2. What is the main purpose of an I/O interface?

A) To increase the speed of the CPU. B) To connect the CPU to main memory. C) To manage the flow of data between the CPU and peripheral devices. D) To execute program instructions.

3. Asynchronous data transfer is characterized by:

A) A fixed clock signal synchronized between sender and receiver. B) The sender and receiver using separate clock signals. C) Data transfer only occurring when the CPU is idle. D) The use of Direct Memory Access (DMA).

4. In asynchronous data transfer, what is the function of control lines like 'Strobe' and 'Ready'?

A) To specify the memory address. B) To synchronize the data transfer between sender and receiver. C) To control the CPU's clock speed. D) To enable interrupt handling.

5. Which mode of transfer involves the CPU actively checking the status of the I/O device before transferring data?

A) Interrupt-Initiated I/O B) Direct Memory Access (DMA) C) Programmed I/O D) Memory-Mapped I/O

6. In Programmed I/O, who is responsible for initiating and controlling the data transfer?

A) The peripheral device itself. B) The Direct Memory Access (DMA) controller. C) The Central Processing Unit (CPU). D) The I/O interface controller.

7. What is a key disadvantage of Programmed I/O?

A) It requires complex hardware interfaces. B) It is inefficient because the CPU spends a lot of time polling. C) It cannot handle high-speed data transfers. D) It requires a separate clock for each I/O device.

8. Interrupt-Initiated I/O allows a peripheral device to:

A) Directly access main memory without CPU intervention. B) Signal the CPU when it is ready for data transfer. C) Control the CPU's clock speed. D) Perform arithmetic operations independently.

9. When an interrupt occurs, what is the typical first step performed by the CPU?

A) Continue executing the current instruction. B) Save the current program counter and processor status. C) Immediately fetch data from the I/O device. D) Reset the interrupt signal.

10. What is the purpose of an Interrupt Service Routine (ISR)?

A) To manage the CPU's cache memory. B) To handle the specific event that caused the interrupt. C) To load new programs into memory. D) To control the power supply to peripheral devices.

11. What is interrupt latency?

A) The time taken to complete an interrupt service routine. B) The time from when an interrupt is generated to when the ISR begins execution. C) The time required for the CPU to fetch an instruction. D) The total time a peripheral device is busy.

12. Which mechanism allows multiple devices to request an interrupt, and the system prioritizes them?

A) Direct Memory Access (DMA) B) Programmed I/O C) Priority Interrupt Controller D) Asynchronous Transfer

13. In a priority interrupt system, what happens when a higher-priority interrupt occurs while a lower-priority interrupt is being serviced?

A) The lower-priority interrupt is ignored. B) The CPU completes the lower-priority ISR and then handles the higher-priority interrupt. C) The CPU suspends the lower-priority ISR and services the higher-priority interrupt. D) The system crashes.

14. What is the primary advantage of using a Priority Interrupt Controller?

A) It eliminates the need for I/O interfaces. B) It allows the CPU to focus on critical tasks by handling interrupts in order of importance. C) It increases the clock speed of the CPU. D) It reduces the amount of RAM required.

15. What does DMA stand for in computer architecture?

A) Direct Memory Access B) Digital Memory Allocation C) Data Management Architecture D) Dynamic Memory Allocation

16. The main benefit of Direct Memory Access (DMA) is:

A) To allow the CPU to perform complex calculations. B) To reduce the burden on the CPU by allowing peripherals to transfer data directly to/from memory. C) To increase the speed of program execution. D) To manage the operating system's processes.

17. Which component is essential for DMA to function?

A) Interrupt Service Routine (ISR) B) Central Processing Unit (CPU) C) DMA Controller D) Programmed I/O Controller

18. In DMA transfer, what is 'cycle stealing'?

A) The DMA controller stealing data from the peripheral. B) The DMA controller temporarily taking control of the system bus from the CPU to transfer data. C) The CPU stealing cycles from the DMA controller. D) An unauthorized access to memory.

19. Which type of DMA transfer is most efficient for high-speed peripherals?

A) Burst Mode DMA B) Cycle Stealing DMA C) Programmed I/O D) Interrupt-Initiated I/O

20. In Burst Mode DMA, the DMA controller:

A) Transfers data one word at a time. B) Transfers a block of data continuously without interruption from the CPU. C) Waits for CPU permission for each word transfer. D) Only transfers data when the CPU is idle.

21. Serial communication involves:

A) Transferring multiple bits simultaneously over separate lines. B) Transferring bits one after another over a single line. C) Transferring data using a parallel bus. D) Synchronized data transfer using a shared clock line.

22. Which is a common application of serial communication?

A) Connecting multiple hard drives to a motherboard. B) Connecting a keyboard or mouse to a computer. C) Transferring large files between two internal storage devices. D) High-speed graphics card communication.

23. What is the primary advantage of serial communication over parallel communication for long distances?

A) Higher data transfer rates. B) Fewer wires are required, reducing cost and complexity. C) Simpler error detection mechanisms. D) Lower power consumption.

24. In serial communication, what is the role of a UART (Universal Asynchronous Receiver/Transmitter)?

A) To manage DMA transfers. B) To convert parallel data from the CPU to serial data for transmission and vice versa. C) To prioritize interrupts. D) To synchronize data between sender and receiver using a shared clock.

25. Which protocol is commonly used for synchronous serial communication?

A) RS-232 B) USB C) SPI D) I2C

26. What is a key characteristic of synchronous serial communication?

A) Each data transfer requires separate start and stop bits. B) A shared clock signal synchronizes data transmission between sender and receiver. C) The CPU continuously polls the device for data. D) Data is transferred asynchronously.

27. RS-232 is a standard primarily used for:

A) High-speed internal bus communication. B) Connecting peripherals like modems and terminals (often asynchronous). C) Graphics card interfaces. D) Network interface cards.

28. Which of the following is an example of a parallel interface?

A) USB B) Ethernet C) Centronics (for printers) D) HDMI

29. What is the main difference between memory-mapped I/O and I/O-mapped I/O?

A) Memory-mapped I/O uses separate I/O instructions, while I/O-mapped I/O uses memory instructions. B) Memory-mapped I/O shares the same address space as memory, while I/O-mapped I/O uses a separate address space. C) Memory-mapped I/O is always asynchronous, while I/O-mapped I/O is always synchronous. D) Memory-mapped I/O requires DMA, while I/O-mapped I/O uses programmed I/O.

30. In I/O-mapped I/O (also known as port-mapped I/O), the CPU uses specific instructions like 'IN' and 'OUT' to:

A) Access main memory locations. B) Access peripheral device registers. C) Control the system clock. D) Perform arithmetic operations.

31. What is the role of the bus controller in I/O operations?

A) To execute program instructions. B) To manage the flow of data and control signals between the CPU, memory, and I/O devices on the system bus. C) To generate interrupts. D) To perform calculations.

32. A 'handshake' mechanism in I/O transfer typically involves:

A) The CPU sending data without confirmation. B) Control signals exchanged between the I/O device and the CPU/interface to coordinate data transfer. C) The peripheral device initiating the entire transfer. D) A fixed-time delay between transfers.

33. Which of the following is a type of input device?

A) Printer B) Monitor C) Keyboard D) Speaker

34. Which of the following is a type of output device?

A) Scanner B) Microphone C) Plotter D) Mouse

35. What is a common use case for Direct Memory Access (DMA) in modern computers?

A) Executing simple arithmetic operations. B) Transferring data from a hard drive to RAM. C) Handling user input from a keyboard. D) Displaying graphics on a monitor.

36. When an I/O device needs attention from the CPU, it typically uses a(n):

A) DMA request. B) Interrupt signal. C) Bus cycle. D) Clock pulse.

37. Which of the following is NOT a mode of data transfer between CPU and I/O devices?

A) Programmed I/O B) Interrupt-Initiated I/O C) Direct Memory Access D) Cache Memory Access

38. What is the purpose of a 'parity bit' in some serial communication protocols?

A) To increase the data transfer speed. B) To provide a simple mechanism for error detection. C) To synchronize the sender and receiver. D) To encrypt the data.

39. Which interface is designed for high-speed, general-purpose serial communication and connects many types of peripherals?

A) RS-232 B) Parallel Port C) USB (Universal Serial Bus) D) PS/2

40. In the context of I/O interrupts, what is 'interrupt masking'?

A) The process of disabling interrupts temporarily. B) The mechanism for prioritizing interrupts. C) The routine that handles the interrupt. D) The signal sent by the device to the CPU.

41. Which statement best describes the 'Bus Arbitration' process?

A) The CPU deciding which program to run next. B) A mechanism to control which device (CPU, DMA controller) gets access to the system bus at any given time. C) The process of loading data into memory. D) The management of peripheral device drivers.

42. What is the main function of an I/O device controller?

A) To execute machine code instructions. B) To act as an intermediary between the I/O device and the system bus, handling device-specific protocols and data formatting. C) To manage the CPU's cache. D) To store the operating system kernel.

43. Which type of I/O transfer is characterized by the CPU issuing a command to the I/O device and then waiting for it to complete the operation without further CPU involvement until completion?

A) Programmed I/O B) Interrupt-Initiated I/O C) Direct Memory Access D) Memory-Mapped I/O

44. In a daisy-chain priority interrupt system, the interrupt request lines are:

A) Parallel, with each device having its own line. B) Serially connected, with the request passing from one device to the next. C) Connected directly to the CPU's interrupt controller. D) Managed by the DMA controller.

45. What is the primary advantage of using DMA over Programmed I/O for large data transfers?

A) Lower hardware complexity. B) Reduced CPU overhead, allowing the CPU to perform other tasks concurrently. C) Higher interrupt latency. D) Simpler programming model.

46. Which of the following best describes 'memory-mapped I/O'?

A) I/O devices are controlled using specific I/O instructions. B) I/O devices are accessed using the same address space and instructions as memory. C) Data transfer occurs directly between I/O devices and main memory without CPU intervention. D) The CPU polls I/O devices for readiness.

47. What is a common peripheral device that utilizes serial communication?

A) Internal Hard Drive B) Graphics Card C) External Modem D) RAM Module

48. Which term describes the process by which an I/O device signals to the CPU that it requires attention?

A) Polling B) DMA transfer C) Interrupt D) Bus arbitration

49. What is the fundamental difference between serial and parallel data transfer?

A) Serial uses one wire for data, parallel uses multiple wires. B) Serial is always synchronous, parallel is always asynchronous. C) Parallel transfer is faster over short distances, serial is faster over long distances. D) Serial transfers entire blocks at once, parallel transfers bit by bit.

50. In a DMA controller, what information must be provided to initiate a transfer?

A) Only the starting memory address. B) The starting memory address, the number of words to transfer, and the direction of transfer (read/write). C) The CPU's current program counter value. D) The interrupt vector number.

Input-Output Organization - peripheral devices, I-O interface, asynchronous data transfer, modes of transfer, priority interrupt, DMA, serial communication - Online Test

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